Mixed-signal IC Design Engineer
Arago is hiring for the position of Mixed-signal IC Design Engineer in Paris Offices. The listing describes it as a full-time position.
DGJ summary of this job
Our own short read of this listing, built only from the facts it gives. The employer’s original text follows further down.
Arago is hiring for the position of Mixed-signal IC Design Engineer in Paris Offices. The listing describes it as a full-time position.
From the advert, the main requirements are English language skills.
The employer does not state a salary in this listing; the DGJ Country Salary Calculator gives official average pay figures by country.
Benefits mentioned in the advert: pension or retirement plan, paid time off, equity or stock options, bonus and learning budget.
Dev Global Jobs found this job on Arbeitnow on Nov 3, 2026.
- Employer
- Arago
- Location
- Paris Offices
- Job type
- Full-time
- Pay
- Not stated by the employer
- Languages asked
- English
- Found
- Nov 3, 2026 on Arbeitnow
- Employer text
- 579 words, about 3 min to read
- Apply only on the official page (arbeitnow.fr). Dev Global Jobs is not the employer and never asks for a fee.
- Say your level in English plainly (for example B2 or C1).
- Read the employer’s full text below (about 3 min) before you apply.
- Build or check your CV with the free DGJ CV Builder.
About the role
Full text from the employer, as published on Arbeitnow, arranged into sections. Nothing added or removed.
01Meet Arago and the Aragonians
Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors.
Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs.
Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles:
Do great things: we deliver work we’re proud to sign our name to.
High velocity: speed matters. We move quickly, one step at a time.
One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie.
Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders.
02What you’ll do
Design, integrate, and deliver high-performance digital subsystems within mixed-signal ICs, enabling control, calibration, and high-speed data movement in analog-centric environments, owning the flow from RTL to physical implementation and tape-out.
03Responsibilities
Design and verify digital subsystems that interface directly with high-speed analog and mixed-signal circuits, including calibration engines, control FSMs, data converters, and multiplexing logic.
Contribute to the design of analog components at the digital-analog interface: calibration circuits, DACs/ADCs, comparators, and others.
Integrate and customize external IP blocks (e.g., GPIOs, LVDS I/Os, serial interfaces), ensuring compliance with analog signal and timing requirements.
Lead the digital implementation flow for mixed-signal blocks: from RTL to synthesis, floorplanning, P&R, timing closure, physical signoff, and tape-out.
Collaborate closely with analog, layout, and system teams to co-optimize digital-analog boundaries, resolve cross-domain issues, and ensure robust high-speed performance.
Contribute to the development of high-speed serial I/O subsystems, experience in the design and implementation of SerDes blocks is a significant advantage.
Language: English at a proficient level. French is a plus.
04Required Skills and Experience
Strong experience in digital RTL design (Verilog/SystemVerilog), particularly for mixed-signal systems involving high-speed calibration/control loops, converters, multiplexers, and serial/parallel data paths.
Experience with analog IC development environments (Virtuoso or equivalent).
Deep understanding of digital-analog integration challenges, including timing closure, noise coupling, clock domain crossing, and analog-aware floorplanning in high-speed environments.
Proven ability to drive digital blocks from design through verification, synthesis, floorplanning, P&R, and tape-out, especially in the context of analog or RF ICs.
Skilled in integrating and adapting external IPs such as GPIOs, LVDS, SPI/I²C interfaces; experience with high-speed serializers/deserializers (SerDes) is a highly valued plus.
Proficient with industry-standard EDA toolchains for both front-end (design/verification) and back-end (physical implementation), with a strong grasp of mixed-signal layout constraints.
05Pay and benefits
Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions.
Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers).
Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location.
Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays.
Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive.
Reimbursement of 50% of the public transport subscription fee.
A high-paced, multicultural (with 9 nationalities), and engineering-led environment.
Find Jobs in France on Arbeitnow
Ask CSI about this job
Answers link to jobs and tools on Dev Global Jobs.
Review Dev Global Jobs
Used this site to find a job? Tell other job seekers what worked and what did not.