Physical Verification Engineer
Salience Labs is hiring for the position of Physical Verification Engineer in Oxford, United Kingdom. The listing describes it as a full-time position.
DGJ summary of this job
Our own short read of this listing, built only from the facts it gives. The employer’s original text follows further down.
Salience Labs is hiring for the position of Physical Verification Engineer in Oxford, United Kingdom. The listing describes it as a full-time position.
From the advert, the main requirements are 3+ years of experience.
The advert mentions Python, Linux and Git among the skills and tools for this role.
The employer does not state a salary in this listing; DGJ Insight below shows an official pay benchmark for the place where one exists.
Visa sponsorship is not mentioned. Applicants from outside United Kingdom should check the official work permit route before applying.
Dev Global Jobs found this job on Arbeitnow on Nov 4, 2026.
- Employer
- Salience Labs
- Location
- Oxford, United Kingdom
- Job type
- Full-time
- Pay
- Not stated by the employer
- Experience asked
- 3+ years
- Found
- Nov 4, 2026 on Arbeitnow
- Employer text
- 322 words, about 1 min to read
- Apply only on the official page (arbeitnow.co.uk). Dev Global Jobs is not the employer and never asks for a fee.
- Compare your own experience with the 3+ years the advert asks for, and show it clearly near the top of your CV.
- Mirror the skills the advert names (Python, Linux and Git) in your CV where you really have them; applicant tracking systems look for these words.
- Read the employer’s full text below (about 1 min) before you apply.
- Build or check your CV with the free DGJ CV Builder.
DGJ Insight
Our own data about this role and place, from official statistics and our live job index.
Source: OECD Average annual wages, 2025
UN living-cost index for United Kingdom (ICSC post adjustment 76.4), as of 1 Oct 2026.
Source: ICSC post adjustment classifications (icsc.un.org)
- Skilled Worker visa: Job offer from a licensed sponsor at the required skill and salary level; English requirement
- Health and Care Worker visa: Eligible health and social care roles with a licensed sponsor
- Global Talent visa: Endorsement as a leader or potential leader in a listed field
Official routes: UK Visas and Immigration (GOV.UK)
About the role
Full text from the employer, as published on Arbeitnow, arranged into sections. Nothing added or removed.
01About us
Salience Labs is building an industry-defining approach to optical circuit switching for AI infrastructure, engineered for real latency reduction and cost savings. We're moving towards real-world deployment, and joining at this stage means genuine ownership over that next chapter, working alongside a highly technical team on one of the most consequential problems in AI infrastructure today.
02About the Role
We’re looking for a Physical Verification Engineer to drive DRC/LVS signoff for our integrated circuit and photonic integrated circuit (PIC) designs. You’ll work at the intersection of electronic and photonic design, running and debugging verification flows against foundry PDKs and helping keep our tapeouts clean.
03What You’ll Do
Run and debug physical verification (DRC, LVS, extraction) on IC and photonic IC layouts
Debug LVS/DRC discrepancies, including port mismatches, hierarchy mismatches, and device recognition issues
Read, manipulate, and QA GDS/OASIS layout data
Maintain and extend verification runsets and rule decks
Build Python/Tcl/shell tooling to automate verification flows and triage error reports
Maintain verification libraries and runsets under version control, with controlled release processes
Handle third-party and foundry IP with care, following licensing terms
Work with design, layout, and CAD teams to close out verification issues ahead of tapeout
Document known issues, workarounds, and runset changes
04What You Bring
Required
3+ years of hands-on physical verification experience in IC design
Practical experience with Siemens Calibre and/or Synopsys ICV for DRC/LVS signoff
Experience with custom/analog layout tools such as Cadence Virtuoso or Synopsys CustomCompiler
Strong working knowledge of GDS/OASIS formats and LVS concepts
Proficiency with Linux and scripting in Python, Tcl, or shell
Experience managing rule decks, runsets, or libraries under version control (e.g., Git)
Ability to independently debug complex hierarchical netlist and layout issues
Strong written communication for documenting root causes and fixes
Nice to have
Photonic IC verification experience
Experience with Verilog/SystemVerilog netlists
Exposure to foundry PDK qualification
Experience building internal automation to scale verification
Find Jobs in United Kingdom on Arbeitnow
Ask CSI about this job
Answers link to jobs and tools on Dev Global Jobs.
Review Dev Global Jobs
Used this site to find a job? Tell other job seekers what worked and what did not.