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Technology

Physical Design Engineer - Innovus Experience, 4 Yrs

Proziod AnalyticsMadivala, Bangalore, IndiaFull-time₹1,000,000 - ₹1,500,000 per yearPosted Nov 5, 2026

Proziod Analytics has an opening for a Physical Design Engineer - Innovus Experience, 4 Yrs in Madivala, Bangalore, India. The listing describes it as a full-time position.

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DGJ summary of this job

Our own short read of this listing, built only from the facts it gives. The employer’s original text follows further down.

Proziod Analytics has an opening for a Physical Design Engineer - Innovus Experience, 4 Yrs in Madivala, Bangalore, India. The listing describes it as a full-time position.

Pay stated in the listing: ₹1,000,000 - ₹1,500,000 per year.

Visa sponsorship is not mentioned. Applicants from outside India should check the official work permit route before applying.

Dev Global Jobs found this job on Adzuna on Nov 5, 2026.

Employer
Proziod Analytics
Location
Madivala, Bangalore, India
Job type
Full-time
Pay
₹1,000,000 - ₹1,500,000 per year
Found
Nov 5, 2026 on Adzuna
Employer text
74 words, about 1 min to read
Before you apply
  • Apply only on the official page (adzuna.in). Dev Global Jobs is not the employer and never asks for a fee.
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DGJ Insight

Our own data about this role and place, from official statistics and our live job index.

Updated Nov 8, 2026
Pay benchmark
Mean monthly earnings, India
$256 average / month

Source: ILOSTAT mean nominal monthly earnings, 2025

Cost of living · India
73.4 vs New York = 100

UN living-cost index for India (ICSC post adjustment 28.9), as of 1 Oct 2026.

Source: ICSC post adjustment classifications (icsc.un.org)

Work permit route
  • Employment visa: Skilled professionals with contract and minimum salary

Official routes: Indian Visa Online (Ministry of Home Affairs)

Job description

About the role

Full text from the employer, as published on Adzuna, arranged into sections. Nothing added or removed.

Physical Design engineer - Innovus Experience, 2 Exp- 4 NP- Immediate Job Roles Physical Design Planning : Floor planning: Create a floorplan that defines the placement of different functional blocks and components on the semiconductor die to optimize power, performance, and area (PPA). Placement: Place and optimize logic cells, memory elements, and other IP blocks on the chip according to the floorplan. Balance trade-offs between area, timing, and power consumption. Clock Tree Synthesis (CTS):…

This is a short excerpt. Read the full ad at the source (Adzuna)

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