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RTL Design Engineer, Networking / NoC

OpenAISan FranciscoFull-timeSalary not listed · Typical pay in United StatesPosted Nov 10, 2026

This listing is for a RTL Design Engineer, Networking / NoC role at OpenAI, as a remote role open to applicants in United States. It is listed as a full-time position.

Written by Dev Global Jobs

DGJ summary of this job

Our own short read of this listing, built only from the facts it gives. The employer’s original text follows further down.

This listing is for a RTL Design Engineer, Networking / NoC role at OpenAI, as a remote role open to applicants in United States. It is listed as a full-time position.

The advert names networking as a skill for this role.

No salary is given in this listing, so check the official pay figures in the DGJ Insight section below where they exist.

Dev Global Jobs found this job on Ashby on Nov 10, 2026.

Employer
OpenAI
Location
Remote (United States)
Job type
Full-time
Pay
Not stated by the employer
Found
Nov 10, 2026 on Ashby
Employer text
861 words, about 4 min to read
Skills named in the advert
networking
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DGJ Insight

Our own data about this role and place, from official statistics and our live job index.

Updated Nov 10, 2026
Pay benchmark
Average wage, United States
$86,977 average / year

Source: OECD Average annual wages, 2025

Job description

About the role

Full text from the employer, as published on Ashby, arranged into sections. Nothing added or removed.

About the Team

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. The team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.

01About the Role

We’re looking for an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. In this role, you'll work across architecture, microarchitecture, and RTL implementation, translating complex system and performance requirements into efficient, scalable hardware designs.

You'll collaborate closely with silicon architects, hardware and software engineers, verification, and physical design teams to co-design hardware solutions optimized for demanding AI workloads. This is a hands-on engineering role with opportunities to influence architectural decisions, drive microarchitecture development, and own RTL design from early concept through implementation and integration.

We're particularly interested in engineers with experience in Network-on-Chip (NoC), networking, interconnect architectures, or high-performance data movement, though the role encompasses broader RTL design and hardware co-design challenges.

In this role, you will:

  • Design and implement high-performance RTL for next-generation AI accelerator silicon, from microarchitecture definition through implementation and integration.
  • Collaborate with architecture and software teams to translate system-level requirements into efficient hardware microarchitectures.
  • Drive hardware/software co-design efforts to optimize performance, power, area, and scalability for AI workloads.
  • Develop and optimize RTL for complex datapaths, control logic, interconnects, and other critical silicon subsystems.
  • Evaluate architectural and microarchitectural tradeoffs across bandwidth, latency, throughput, and resource utilization.
  • Partner with design verification and formal verification teams to ensure functional correctness, develop verification strategies, and debug complex design issues.
  • Work closely with physical design teams to optimize RTL for synthesis, timing closure, power, and area.
  • Contribute to architecture reviews, design specifications, and cross-functional discussions to influence future silicon designs.
  • Support block-level and SoC-level integration, debugging, and performance optimization.

You might thrive in this role if you:

  • Have strong hands-on experience with ASIC RTL design and microarchitecture development using SystemVerilog or Verilog.
  • Have experience designing and implementing complex digital hardware blocks, from architecture and specification through RTL development and verification.
  • Understand hardware architecture and microarchitecture tradeoffs, including performance, power, area, latency, and throughput.
  • Have experience collaborating across architecture, software, verification, and physical design teams to develop optimized hardware solutions.
  • Can reason about complex hardware systems, identify performance bottlenecks, and translate architectural requirements into efficient RTL implementations.
  • Have experience with synthesis, timing closure, and physical implementation considerations.
  • Enjoy working on ambiguous, technically challenging problems and taking ownership of designs from concept through integration.
  • Bring experience with Network-on-Chip (NoC), networking, interconnect fabrics, packet-based architectures, or high-bandwidth data movement systems.
  • Experience with AI accelerators, high-performance computing, or hardware/software co-design is a plus.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.

For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement https://cdn.openai.com/policies/eeo-policy-statement.pdf.

Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates.

For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information.

In addition, job duties require access to secure and protected information technology systems and related data security obligations.

To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form https://form.asana.com/?d=57018692298241&k=5MqR40fZd7jlxVUh5J-UeA. No response will be provided to inquiries unrelated to job posting compliance.

We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link https://form.asana.com/?k=bQ7w9h3iexRlicUdWRiwvg&d=57018692298241.

OpenAI Global Applicant Privacy Policy https://cdn.openai.com/policies/global-employee-and-contractor-privacy-policy.pdf

At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.

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